Chandler, United States of America Hybrid

PowerLattice is hiring a Power Delivery Solution Architect

About the Role

Role Overview

As a Power Delivery Solution Architect, you will play a central technical role in advancing the adoption of our chiplet-based power delivery network solution. You'll work directly with leading semiconductor customers to integrate our technology into high-performance GPU and CPU SoC designs, ensuring optimal power integrity and system performance.

Key Responsibilities

  • Guide customers in designing power delivery solutions using our chiplet technology for advanced SoC architectures
  • Support optimization of power delivery networks using our proprietary design tools and kits
  • Collaborate across the customer lifecycle—from early simulation and modeling to physical implementation and system validation
  • Collect and analyze technical feedback to inform product improvements and enhance customer enablement
  • Serve as the primary technical liaison for tier-one customers, ensuring clear communication and alignment
  • Handle sensitive design data with the highest level of confidentiality and professionalism

Qualifications

You bring extensive experience in power and signal integrity for complex SoC designs. Your background includes hands-on work with electrical modeling, simulation workflows, and advanced packaging technologies.

  • 8+ years focused on power integrity, signal integrity, or related fields for high-performance SoCs
  • Proficient in PI/SI simulation tools and analysis methodologies
  • Experience extracting, building, and validating electrical models for SoC packages
  • Strong knowledge of package-level power and signal integrity, including substrates, interposers, and 2.5D/3D integration
  • Proven ability to debug issues across simulation and lab testing environments
  • Excellent communication skills with a track record of engaging technical teams at customer sites
  • Self-driven with strong problem-solving skills and the ability to operate independently

Preferred Experience

  • Work history at a major processor or ASIC developer in power or signal integrity roles
  • Leadership experience in engineering or technical project management
  • Hands-on lab experience with power integrity test setups and instrumentation
  • Familiarity with advanced packaging platforms such as CoWoS and 2.5D integration

Work Environment

This is a hybrid role with primary locations in Chandler, AZ, Vancouver, WA, and Silicon Valley, CA. Candidates are expected to be onsite at least three days per week. Exceptional candidates based in Silicon Valley may qualify for increased remote flexibility.

Compensation & Benefits

Base salary ranges from $180,000 to $250,000, depending on experience. The package includes stock options and a comprehensive benefits plan covering health, dental, vision, and 401(k) contributions.

Culture & Expectations

You will thrive in a fast-moving, entrepreneurial environment where ownership and initiative are expected. Success in this role means anticipating technical challenges, guiding both internal teams and customers, and contributing directly to product evolution. We value technical depth, discretion, and the ability to drive solutions with minimal oversight.

Required Skills
PI/SI simulationSoC package electrical modelingPower integrity analysisSignal integrity analysisSimulation flow automationElectrical test instrumentationAdvanced packaging (2.5D/3D)Substrate and interposer designHigh-performance SoC power delivery PI/SI simulationSoC package electrical modelingPower IntegritySignal IntegrityAdvanced Packaging2.5D/3D IntegrationCoWoSHigh-Performance SoCsSubstrate DesignInterposer Modeling
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About company
PowerLattice

PowerLattice is reimagining power delivery for next-generation AI accelerators with the industry's first power delivery chiplet. The company tightly integrates power and compute, delivering power precisely where and when it’s needed to achieve breakthrough performance, efficiency, and scalability for AI and data center infrastructure.

PowerLattice’s solution breaks through the AI “power wall” by integrating voltage regulation directly into the processor package, drastically reducing power loss and noise. This enables more than 50% reduction in effective compute power needs, cooler runtime, and up to 2X or more raw performance uplift under fixed power budgets.

The company’s chiplet architecture is based on its proprietary Rainier micro-IVR technology, combining miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer in a vertical, scalable design. This allows seamless adaptation to any SoC power topology and supports flexible integration into various packaging schemes.

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Job Details
Category embedded
Posted 3 months ago