As a Component Design Engineer, you will lead the development of Design for Test (DFT) circuits and firmware for cutting-edge 3DNAND flash memory technology. Your work will focus on improving test efficiency, increasing coverage, and accelerating time-to-market through innovative circuit design and automation.
Key Responsibilities
- Design and implement DFT circuitry to support advanced testing methodologies in 3DNAND architectures
- Develop and optimize complex DFT firmware to reduce test duration and enhance diagnostic precision
- Validate circuit functionality through simulation and formal verification techniques
- Collaborate with design, product engineering, and manufacturing teams to define and refine test modes
- Lead first silicon debug efforts, identifying and resolving DFT-related issues
- Perform layout design and circuit checks to ensure physical and electrical integrity
- Characterize and evaluate semiconductor components through prototyping and iterative testing
- Document design specifications and contribute to cross-functional project planning
- Analyze logic diagrams and product requirements to guide test strategy development
- Apply engineering judgment to solve complex pre- and post-silicon challenges
Qualifications
Candidates should have a Bachelor’s degree with at least seven years of experience or a Master’s degree with five years in logic design. Proficiency in RTL coding and firmware development is essential. Experience with simulation tools such as runsim and Verdi, as well as familiarity with HSPICE or XA, is required. Scripting expertise in Perl, Tcl, and Make is expected, along with hands-on experience using schematic editors like Virtuoso.
Preferred candidates will have exposure to layout tools and the ability to independently troubleshoot silicon-level issues.
Work Environment
This hybrid role requires 2–3 days per week onsite in San Jose or Sacramento. You’ll work within a culture that values innovation, collaboration, and technical excellence. The organization supports a diverse, inclusive workplace where engineers are empowered to shape the future of memory technology.
Compensation and Location
The salary range for this position is $121,280 to $221,700. Engineers will have the opportunity to work in dynamic tech hubs with access to rich cultural offerings, a thriving arts community, and Sacramento’s renowned Farm-to-Fork culinary scene.
